Model — Valentina Ttl

module mux2_ttl ( input a, b, sel, output y ); wire n_sel, and1, and2; not #1 (n_sel, sel); // TTL inverter with 1ns delay and #2 (and1, a, n_sel); // TTL AND gate and #2 (and2, b, sel); or #2 (y, and1, and2); // TTL OR gate endmodule

is sometimes used as a descriptor for specific modeling niches. TTL Model Girl valentina TTL model