Synopsys Design Compiler Tutorial 2021 -

set_load 0.05 [all_outputs]

Without constraints, DC produces a minimal-area, slow-as-molasses netlist. For 2021, use the SDC (Synopsys Design Constraints) format. synopsys design compiler tutorial 2021

# .synopsys_dc.setup set search_path [list . /home/designs/rtl /tools/libs/SAED32_EDK/lib/stdcell] set target_library "saed32nm_tt_1p05V_25C.db" set link_library [list "*" $target_library saed32nm_io.db] set symbol_library "saed32nm.sdb" set synthetic_library "dw_foundation.sldb" set_load 0

To move from "tutorial" to "expert," adopt these 2021-specific practices: set_load 0.05 [all_outputs] Without constraints